Physical Design Engineer

Added: 08/10/2019

REF: 652

Contract: Permanent

Location: Boston, Massachusetts, United States

Role: Physical Design Engineer

Location: Boston MA

Comp: 150-170k + Equity

 

The Company  

Founded in 2017, this Boston MA based hardware + software co-design company focused on special-purpose computing, building optical chips that empower the next generation of high-performance computing tasks. By processing information with light, these next gen chips offer ultra-high speed, low latency, and low power consumption that has not been possible in traditional electronic architectures.  

 

The Project

Recent investment funding. Building next phase of workable demos. As a hardware + software co-design company focused on special-purpose computing, we are seeking extraordinarily talented computer scientists, physicists, mathematicians, and engineers who want to push the limits.

 

The Role

Physical Design Engineer. Owning the physical build / Architecture. Working hand in hand with logical team. We are seeking extraordinarily talented computer scientists, physicists, mathematicians, and engineers who want to push the limits.

 

2 Positions Available:

P&R Place and Route Role Specialist - Senior Physical Design Engineer

 

  • Create high performance, high frequency digital and mixed signal designs and drive from synthesis to tapeout.

  • Bring to life a robust place and route flow/methodology that handles the challenges of power grid infrastructure, design floor planning, Clock and Signal Routing, STA analysis and closure, and backend design verification.

  • Work with team members across all disciplines to optimize all physical aspects of the design

 

Preferred Qualifications: P&R Design Engineer

  • BS or higher in Electrical/Computer Engineering degree.
  • Minimum of 5 years experience in P&R and Physical Design deep sub-micron technologies, at 1GHz or higher clock frequencies. 10+ years experience is a bonus.
  •  Solid knowledge of Synthesis and P&R Methodologies/Flows.
  • Experience with industry-standard EDA tools with emphasis on Synthesis and P&R. Familiarity with the Cadence tool-suite is a plus.
  • Experience with SoC challenges such as multiple clock, multiple power domains is a plus.
  • Proficiency in scripting languages (TCL is a plus).
 

Static Timing Analysis Specialist - STA Design Engineer

  • Develop a Static Timing Analysis [STA] methodology/flow for ASICs, SoCs suitable for multiple clock and power domains.

  • Work with stakeholders in all disciplines to determine relevant timing collateral such as timing/process corners.

  • Run fullchip signoff timing analysis. Drive timing convergence with the physical design team.

  • Work with EDA Tool Venders to help resolve any issues with the timing tools.

  • Work with team members across all disciplines to optimize all physical aspects of the design.

  • Define back-end physical design methodology for ASIC tapeouts

  •  Define ASIC clocking methodology & rules for ASIC blocks and full-chip and define and own clocking architecture, reset and power sequencing strategy for ASICs  

Preferred Qualifications:

  • BS or higher in Electrical/Computer Engineering degree.

  • Minimum of 5 years experience in STA and Timing Convergence in deep sub-micron technologies, at 1GHz or higher clock frequencies.  

  • Solid knowledge of STA Methodologies/Flows.

  • Experience with industry-standard EDA tools with emphasis on Static Timing Analysis.

  • Familiarity with the Cadence tool-suite is a plus.

  • Proficiency in scripting languages (TCL is a plus).

 

Why Work Here:  

This is an opportunity to join an exciting tech startup who are revolutionizing integrated computer hardware and software that will be the driving force behind next gen advanced computer processing!

 401(k) Match

Health Benefits

Shared Equity

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